ARIN22 · Layer 0 · Deterministic Kernel

A deterministic computational core for systemic risk.

A class-routed deterministic acceleration layer — deterministic where it provably can be, Monte-Carlo-challenged where it must be, every verdict hash-logged. ARIN22 is a US trademark name (registration pending) for the deterministic risk-core; the construction is a protected trade secret. Embeddable beside Aladdin, Bloomberg, Murex, and MSCI — not a replacement for full-stack risk platforms.

US trademark name (registration pending) · ~99 µs at D=4 synthetic · ~0.3 ms at D=200 real portfolios · 0.035% canonical / D=200 p95 0.28% · max 0.90% · Enterprise Wave: 8.8 B paths/backend · 10M lane: internal Market Readiness canon; aggregate formula under reconciliation · CRN 99.9 PASS.

S1.5 · Evidence status taxonomy · claim posture

Measured challenger, bounded claims.

ARIN22 is a measured, artifact-bound risk-compute challenger with strict claim boundaries. The strongest current claim is operational reproducibility and latency-governed evidence; model-validation claims remain bounded until realised evidence and external replication mature.

ARIN22 is

  • A risk-compute and governance kernel.
  • A challenger layer beside incumbent systems.
  • A hash-bound evidence and replay layer.

ARIN22 is not

  • Not an exchange execution venue.
  • Not a market-maker pricing stack.
  • Not a full replacement for Aladdin / Bloomberg / Murex / MSCI.
  • Not an externally attested production risk system.
Status Meaning Public claim boundary
MEASUREDArtifact-bound internal evidence.Publishable inside the stated workload envelope.
REVIEW_ONLYEngineering evidence, not external validation.Disclose as diligence material, not external attestation.
RESEARCH_ONLYChallenger lane, not production claim.Supports research posture; cannot promote production parity.
PENDINGPlanned benchmark or external replication.No public performance claim until artifact-bound.
NOT CLAIMEDExplicit boundary.Used to prevent implied attestation or client validation.

Operational gates validate runtime, replayability, drift control, and evidence custody. They do not by themselves establish predictive model validity or regulatory backtest maturity.

Matte cube with brass seam, ARIN22 Layer 0 preview
ARIN22 · Layer 0 · Deterministic Kernel Measured challenger
Evidence lane Status Artifact ID Boundary
Tick replayMEASUREDartifact:FINAL_H100_EVIDENCE_INDEX_20260530Self-run, not STAC.
Pre-trade gateMEASURED / REVIEW_ONLYartifact:pretrade_replay_manifest@sha256:...Not live execution.
Quant challengerRESEARCH_ONLYartifact:quant_library_challenger_20260612Not production Greeks parity.
Shadow ledgerPENDING / ARMEDartifact:shadow_ledger_statusNot 250/250 realised-validation pass.
Evidence surface Status Release boundary
Shadow LedgerARMEDOutcome-ingestion contract active; release promotion remains gated.
Realised evidenceDEVELOPINGRecorded outcomes are not yet mature enough for public realised-validation claims.
250/250 validation floorNOT CLAIMEDNo regulatory backtest maturity claim until the observation floor is met.
Surface Visible content
Public pageEnvelope, evidence status, boundaries, and non-claim discipline.
NDA packRun SHA, hardware fingerprint, full q999 distribution, artifact hashes, and replay bundle.
Trade secretInternal construction details remain protected.

S2 · Signature proof

The evidence is the page hero.

Three quiet proofs. A worst-tail CPU↔GPU parity scatter that lies exactly on the y = x line. A May 24-million-tick latency histogram retained as lineage, explicitly superseded by the 2026-05-30 canon lane. And a determinism check across a thousand fresh processes that produces a single hash.

CRN 99.9 GPU↔CPU parity scatterOne hundred worst-tail cases, 100 million paths per backend. All points lie on the y = x reference; R² 1.0000, RMSE 0.0000, Δmax 0.000 bp.0%0%1%1%2%2%3%3%4%4%5%5%CPU result · CVaR 99.9 deviationGPU result · CVaR 99.9 deviation

CRN 99.9 GPU↔CPU parity

R² 1.0000 · RMSE 0.0000

100 worst-tail cases · 100 M paths per backend · Δmax 0.000 bp · PASS. Regression y = 1.0000·x. Every dot lies on the reference line.

Underlying table · 6-of-100 sample
CaseCPU CVaR 99.9GPU CVaR 99.9Δ bp
WT-0010.010%0.010%0.000
WT-0200.018%0.018%0.000
WT-0400.025%0.025%0.000
WT-0600.031%0.031%0.000
WT-0800.040%0.040%0.000
WT-1000.050%0.050%0.000
Tick-replay latency histogramMay 24-million tick replay lineage, 8×H100, NVIDIA Innovation Lab. Shown for distribution shape only; superseded by the 2026-05-30 canon lane: p99 0.44–0.46 ms, p999 0.653 ms.0.0 ms0.3 ms0.6 ms0.9 ms1.2 msMay p99 · 0.625 msMay p999 · 0.710 msTick-to-decision latencyDensity (N = 24,000,000)

Tick-replay latency · lineage exhibit

May p99 0.625 · p999 0.710 ms · superseded by 05-30 canon

N = 24,000,000 · Run 11/12 · 8×H100 · NVIDIA Innovation Lab · May 2026 lineage. Shown for distribution shape only; headline canon is p99 0.44–0.46 ms / p999 0.653 ms on the 10 M-update lane.

May superseded percentiles
QuantileLatencySample
p500.388 ms24,000,000
p900.524 ms24,000,000
p990.625 ms24,000,000
p9990.710 ms24,000,000
1 hash
Unique digest across the population
A single canonical hash emerges from a thousand independent runs — bit-exact reproducibility, end-to-end.
1,000 repeats
Fresh processes, cold caches
Every run is a fresh OS process; nothing carries state. The kernel is a function, not a session.
0.0% drift
Output divergence across repeats
Zero observed drift — no floating-point reordering, no nondeterministic reductions, no sampler-dependent paths.

Deterministic where it publishes. Monte-Carlo-challenged where it must be.

PASS lane · Challenger lane · fail-closed.

S3 · The challenge

Why a deterministic core matters.

Stale risk evidence changes the decision. ARIN22 reduces dependence on brute-force path enumeration within published workload envelopes. The sections below separate compute capability, measured performance and integration scope. The construction remains a protected trade secret.

S4 · CPU posture

Kernel correctness is CPU-bound. GPU is for scale.

The kernel validates identically on a commodity ARM CPU and an 8×H100 cluster. Every result is stamped with a hardware fingerprint and a run SHA for cross-environment replay. Precise numerics — µs, speedup×, q999%, fingerprint, run SHA — are released to bank model-risk teams under NDA.

~99 µs
Single kernel call · D = 4 synthetic baseline
Measured on a commodity ARM CPU. D = 200 real portfolios run at ~0.3 ms/call; wall-clock scales sub-linearly with dimension, with accuracy kept inside published lane bands.
Orders of magnitude
vs matched-accuracy MC equivalent
Precise speedup× released under NDA. The CPU envelope sits at the near-100 µs D = 4 call and ~0.3 ms at D = 200 — not a sub-microsecond claim.
< 0.05%
q99.9 deviation vs MC gold-standard · lane-scoped
Canonical lane: max 0.035%. D = 200 high-dimensional lane: p95 0.28% / max 0.90%; no blanket claim across regimes.
No lock-in
Identical answer CPU ↔ GPU
Throughput differs; the answer does not. The kernel does not depend on a specific accelerator.
Bare server chip on graphite board, no visible branding

S5 · Three core capabilities

What the kernel does, in three lines.

Constant-cost compute.

Wall-clock cost shows weak dependence on the equivalent MC path count. Verified across separated lanes: Enterprise Wave v2 — 8,800 cases, 8.8 B paths per backend, zero failures; 10M production-default lane remains the internal Market Readiness canon until its public case × path formula is reconciled.

Adaptive tail controller.

Class-routing holds target accuracy under jumps, regime-shifts, and vol-clustering. Deterministic where it provably publishes; CRN-anchored at 99.9; 10 M MC challenger on hard regimes; no silent degradation.

Cross-asset contagion.

Hidden-channel detection across the covariance and contagion structure. Every verdict is hash-chained; replay is bit-exact under a recorded hardware fingerprint.

S6 · Mode catalogue

One kernel, many class-routed modes.

Six public layers (A–F) are the reviewer-facing projection. The internal catalogue contains 22 modes grouped into eight NDA categories (A–H); only six categories (A–F) are exposed publicly. Each public layer publishes enum-named surfaces a reviewer can audit; the construction sitting beneath them — the protected construction dossier — remains NDA-bound. The published list is the IP boundary.

A · Substrate
Class-routed compute lanes.
Three lanes — never collapsed. Correctness anchors on a commodity ARM CPU; throughput scales to an 8×H100 cluster; multi-tenant traffic is fronted by a gateway lane. The answer is identical across lanes; only throughput differs.
LANE_CPU_COMMODITY_ARMLANE_GPU_8xH100LANE_GATEWAY_P95_400MS
B · Math method
Deterministic where it provably publishes, MC-challenged where it must be.
The deterministic construction is a protected trade secret. What is auditable on the public surface: the CRN-anchored 99.9 parity against a 10 M Monte-Carlo challenger; identical answers across PRNG, Sobol, and LHS samplers; sampler-independence as a published property.
PROTECTED_CONSTRUCTIONVALIDATION_DOSSIERCRN_ANCHOR_99_9MC_CHALLENGER_10MSAMPLER_INDEPENDENCE_PRNG_SOBOL_LHS
C · Routing & governor
A verdict is either deterministic, MC-challenged, or fail-closed — never silent.
Each request is class-routed at evaluation time. Routing is hash-logged with the verdict so an external reviewer can replay the decision path. Negative-control scenarios deliberately fail-closed; there is no silent degradation under regime stress.
CLASS_ROUTING_DETERMINISTICCLASS_ROUTING_MC_CHALLENGERFAIL_CLOSED_NEGATIVE_CONTROLHASH_LOGGED_VERDICT
D · Surface
Workload-shaped, not formula-shaped.
What ships to integrators is a finite set of workload surfaces with published envelopes: intraday tick replay, the pre-trade ALLOW / REVIEW / BLOCK gate, deep-tail CVaR at the 99.9 quantile, and the canonical Enterprise Wave v2 validation pack.
TICK_REPLAY_P99_INTRADAYPRE_TRADE_GATE_ALLOW_REVIEW_BLOCKCVAR_99_9_DEEP_TAILENTERPRISE_WAVE_V2
E · Audit & lineage
Every result is replayable from a hardware fingerprint and a run SHA.
Hash-chained verdicts, hardware fingerprint, and run SHA accompany every public result. Lineage from the V1 aggregate (1.06 T paths) to the v2 canonical pack is preserved in the Layer-1 data room.
HARDWARE_FINGERPRINTRUN_SHA_REPLAYLINEAGE_V1_TO_V2
F · Lifecycle
Closed phases, armed surfaces, suppressed promotions — stated, not implied.
Phase 5 and Run 11/12 are closed. The Shadow Ledger is armed but does not yet meet the 250-observation floor for a realised regulatory backtest pass. EVT 99.9 long-horizon is deliberately suppressed from promotion until evidence catches up.
PHASE_5_CLOSEDRUN_11_12_AUDIT_CLOSEDSHADOW_LEDGER_ARMEDWATCH_SUPPRESSED_EVT_99_9_LONG_HORIZON

Institutional reviewers need a written IP boundary — what is auditable publicly (input → output → hash → lineage) versus what is only auditable under NDA (the how of construction). This catalogue is that boundary.

S7 · Performance envelope

Workload, envelope, scale.

The canonical envelope, end-to-end. Numbers are reproducible from the run SHA and hardware fingerprint released under NDA; the public surface publishes the envelope itself.

WorkloadEnvelopeScale · lane
Intraday tick replay p99 0.44–0.46 ms · p999 0.653 ms N = 10,000,000 · canon 2026-05-30 lane · 8×H100
Pre-trade mixed gate p99 0.85–0.93 ms · p999 1.8–2.5 ms N = 50,000,000 orders · ALLOW / REVIEW / BLOCK verdicts
Enterprise Wave v2 canonical 0 failures 8,800 cases · 8.8 B paths / backend
10M production-default lane internal canon lane · not a replacement for Enterprise Wave lineage Public aggregate withheld until case × path formula reconciles
CRN 99.9 parity PASS · Δmax 0.000 bp 100 worst-tail cases · 100 M paths / backend
10 M MC challenger CVaR 99.9 canonical p95 0.015% · max 0.035% · D=200 lane p95 0.28% / max 0.90% 50 cases × 4 seeds × 10 M paths = 2.0 B reference paths
Estimated acceptance battery 160/160 cells within 5% envelope vs 100M-path reference · median |error| 0.0156% · worst cell 2.72% 40 cases × 10 regimes × 4 metrics · params estimated + hash-frozen pre-join · REVIEW_ONLY
Determinism 1 hash · 0.0% drift 1,000 fresh processes
CPU deterministic kernel ~99 µs at D=4 · ~0.3 ms at D=200 D=4 synthetic baseline · D=200 real portfolios · sub-linear scaling · published accuracy bands

All numbers are public-tier. Precise µs, speedup×, full q999 distribution, hardware fingerprint, and run SHA are released to bank model-risk teams under NDA.

S8 · Validation evidence

Enterprise Wave v2 and the 10M production-default lane.

Two evidence lanes are separated deliberately. Enterprise Wave v2 remains the public canonical pack (8,800 cases / 8.8 B paths per backend). The 10M production-default lane is the internal Market Readiness canon; its public aggregate is withheld until the case × path formula is reconciled. V1 aggregate (the 1.06 T-path headline) is superseded as a headline number; it is preserved as lineage inside the Layer-1 data room.

Enterprise Wave v2
8,800 / 8.8 B · GPU grid + commodity-ARM CPU mirror · bit-exact public pack
10M production-default lane
Internal Market Readiness canon · public aggregate withheld until case × path formula reconciles · separate from Enterprise Wave lineage
CRN 99.9 parity
PASS · 100 worst-tail cases · 100 M paths / backend
10 M MC challenger
CVaR 99.9 · max 0.035% · p95 0.015%
Acceptance battery (Aug 2026)
160/160 within 5% vs 100M-path H100 reference · 10 market regimes incl. jump-mixture, regime-switch, near-singular covariance, crypto-tail · estimated parameters, frozen before every join · every intermediate FAIL published · REVIEW_ONLY, pending production re-run.
Crisis replay (5 events × 15 books)
GFC 2008 → SVB 2023, forecasts cut pre-event, like-for-like vs each method’s own forecasts: CVaR99 covered realized losses 73/75 (historical rolling: 23/75); VaR99 breaches 12/75 vs 54/75 · MEASURED, no-lookahead flags per row.
Tick replay
p99 0.44–0.46 / p999 0.653 ms · N = 10 M canon lane
Pre-trade gate
p99 0.85–0.93 ms · p999 1.8–2.5 ms · 50 M-order canon lane · ALLOW / REVIEW / BLOCK
Determinism
1 hash · 1,000 fresh-process repeats · 0.0% drift
Crypto shock replay
5 shocks × 4 assets · 20 packets · 0 narrative-readback violations · out-of-sample, no leakage
Lineage
V1 aggregate (1.06 T paths) superseded as headline; preserved in Layer 1

Phase 5 closed · Run 11/12 audit closed · negative controls fail-closed · sampler-independent across PRNG / Sobol / LHS.

S8.5 · Behavioral evidence

Proof without construction.

The kernel construction remains protected. Its behavior does not. ARIN22 publishes what a model-risk reviewer needs to inspect: convergence discipline, coupling governance, head-to-head accuracy, replayability, and claim boundaries without exposing protected construction.

Exhibit 1 · Convergence behavior
Run-gated

Terminal-state error declines under composition count.

The public surface discloses the lane discipline: same fixture, same Monte Carlo reference, fresh-process repeats, and a log-log convergence trace. Exact slope table and SHA-bound replay pack are released under NDA.

measured terminal error guide A guide B · NDA slope composition count n, log scale

Artifact discipline: exact run ID, SHA256, input fixture, reference backend, and slope table are model-risk artifacts. Public page shows the behavior contract, not protected construction.

Exhibit 2 · Coupling governance
Run-gated

Commutator pressure is admitted, bounded, and routed.

When cross-domain coupling rises, ungoverned model error rises with it. The operator contract requires adaptive routing and step governance so terminal error remains below the institutional cap or the lane fails closed.

institutional cap ungoverned governed cross-domain coupling strength

Routing rule: deterministic lane first; EVT overlay for tail stress; MC challenger for regime-shift and cascade; fail-closed when evidence is insufficient.

Exhibit 3 · Head-to-head lane table
Artifact-bound rows only

Same task, same reference, no silent promotion of research lanes.

Rows are separated by status. Measured lanes can support public claims inside their boundary. Research and pending rows are disclosed as typed limitations, not marketing promises.

Method Status CVaR / error Wall-clock / scale Replay Evidence note
ARIN22 class-routed Measured 0.035% max, canon lane sub-ms / call 1 hash / 1,000 repeats FINAL_H100_EVIDENCE_INDEX_20260530
GPU Monte Carlo reference Measured reference backend 10M-path D=200 lane seed-bound d200_10m_new_variant_20260531
Chebyshev tensor challenger RESEARCH_ONLY controlled payoff fixtures validated as a challenger lane deterministic not a VaR/CVaR replacement
ARIN22 estimated-config battery REVIEW_ONLY 160/160 within 5% envelope · median 0.0156% CPU lane · 40 oracle cases × 100M paths reference frozen-config receipts + oracle evidence SHA per row battery bundle sha256:a87246763088ca661e112e5b32ecd1fde4e80613e9cca9dc98f7afe19f2928c0
NDA benchmark lanes Pending not promoted until run under canon discipline
Chebyshev tensor-train Pending fair sparse variant not yet public-run
AAD / adjoint RESEARCH_ONLY not a tail engine 1000-factor gradient benchmark · speedup band, not hero number artifact-bound gradient check complements ARIN22; not production Greeks parity

Boundary: measured numbers support the ARIN22 Operator Contract v1 evidence lane. Quant-library challenger lanes complement ARIN22 evidence; they are research-only on the public page, not production Greeks parity, not listed-options pricing attestation, and not a VaR/CVaR replacement. Pending rows are explicitly blocked from public claims until bound to archived artifacts.

The construction is protected. The behavior is auditable: convergence order, coupling governance, head-to-head accuracy, deterministic replay, and hash-bound lineage.

S9 · STAC-inspired wave

GPU lane — MC throughput on 8×H100. Self-run, not STAC-audited.

Built to STAC archetypes, self-run. The four lanes below are the GPU-throughput envelope; independent STAC benchmarking is the deliberate next step.

A2
Options Greeks
14.875 s
M3
Tick analytics
p99 0.501 ms
T1
Pre-trade
p99 1.110 ms
FC
Fail-closed stress gate
p99 0.864 ms

Two worlds, never conflated. Monte-Carlo throughput → GPU lane (scale). Deterministic kernel → commodity CPU (correctness). The GPU lane is where MC throughput is measured; the deterministic kernel is where correctness is anchored. Archive SHA + 77 hashed artifacts available under NDA.

S10 · Claim boundaries

What is claimed. What is not.

Claimed

  • Deterministic where it provably publishes — not a blanket Monte Carlo substitute.
  • CRN-anchored 99.9 parity on the worst-tail subset.
  • 10 M MC-challenger backing on hard regimes with hash-logged routing.
  • Tick p99 0.44–0.46 / p999 0.653 ms on the canon 10 M-update lane.
  • Pre-trade gate p99 0.85–0.93 ms · p999 1.8–2.5 ms on the 50 M-order lane; ALLOW / REVIEW / BLOCK published.
  • Determinism: 1 hash / 1,000 repeats / 0.0% drift.
  • CPU correctness on commodity ARM: ~99 µs at D=4, ~0.3 ms at D=200; 0.035% canonical max / 0.90% D=200 max.
  • Negative controls fail-closed.
  • Sampler-independence across PRNG, Sobol, LHS.

Not claimed

  • Not a realised regulatory backtest PASS — Shadow Ledger ARMED, 250-observation floor not yet met.
  • Not a live-production sign-off at any bank or G-SIB.
  • Not a blanket Monte Carlo substitute.
  • Not EVT 99.9 long-horizon promotable — WATCH_SUPPRESSED.
  • Not STAC-audited — self-run.
  • Not a market-maker pricing service.
  • Not a full-stack platform — embeddable layer beside Aladdin / Bloomberg / Murex / MSCI.
  • Not a production accuracy attestation from the acceptance battery — REVIEW_ONLY until the same battery re-runs green on productionized backend routes.

S11 · Economic value

Five mechanism-anchored drivers.

Per-bank ROI is established during pilot, not asserted up front. Quantification and sensitivity envelope are released under NDA. No headline dollar number.

01

Latency value

Intraday recomputation stays within the published workload envelope; latency is a governance constraint.

Anchor · tick p99 0.44–0.46 ms canon

02

GPU utilisation

An 8×H100 cluster is freed for paths that actually need MC challenge; deterministic work runs on commodity ARM.

Anchor · Enterprise Wave 8.8 B/backend · 10M lane formula withheld

03

Compliance velocity

Hash-chained verdicts bind each review to its recorded input, output and run.

Anchor · 1 hash / 1,000 repeats

04

Decision quality

CRN-anchored tail evidence gives committees a stated accuracy boundary.

Anchor · CVaR 99.9 max 0.035%

05

Audit velocity

Reviewers can replay a recorded run with its hardware fingerprint and compare the receipts.

Anchor · Enterprise Wave 0 failures / 8,800 cases

S12 · Architecture integration

Embeddable beside Aladdin, Bloomberg, Murex, MSCI.

ARIN22 is a layer, not a platform. Three calm integration targets — one for risk platforms, one for trading systems, one for sovereign & central use cases.

Risk platforms
Aladdin / MSCI
Recomputation accelerator beside the existing risk engine. Same input contract, reconciled output comparison, deterministic envelope — replayable deltas instead of implied platform replacement.
Trading systems
Bloomberg / Murex
Pre-trade gate with FIX-level hooks. ALLOW / REVIEW / BLOCK published on a 50 M-order mixed gate: p99 0.85–0.93 ms / p999 1.8–2.5 ms.
Sovereign & central
Macro & sovereign stress
CRN-anchored macro / sovereign stress, written IP boundary, bit-exact replay under a recorded hardware fingerprint.
Pilot entry What happens Output
01 · IngestImport incumbent output or an agreed portfolio fixture.Typed input contract and evidence custody record.
02 · Run challenger laneExecute ARIN22 under the routed lane, with fail-closed behavior preserved.Run SHA, hardware fingerprint, and replay bundle.
03 · CompareCompare deltas, latency, replay hash, and governor decisions.Reconciled output comparison, not platform replacement claim.
04 · Decide claimsSeparate measured, review-only, research-only, pending, and not-claimed outputs.Claim matrix: can claim / cannot claim.

Affiliations: NVIDIA Inception · NVIDIA Innovation Lab · Google for Startups · AWS Activate. ARIN22 is a US trademark name (registration pending); the construction is a protected trade secret. Pre-client diligence-ready with a strong public-portfolio H100 validation package; not externally production-attested.

Verify this page: Data room · Methodology
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